The present invention generally relates to a flash memory device and a method of manufacturing the same, in which a gate dielectric film formed between a floating gate and a control gate is formed by depositing an oxide film and a ZrO2/Al2O3/ZrO2 (ZAZ) film, whereby the reliability of flash memory devices can be improved while securing a high coupling ratio.
In general, a semiconductor memory device is largely classified into a volatile memory and a non-volatile memory.
The volatile memory includes Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). The volatile memory has the properties that data can be input and retained when being powered, but data become volatile and cannot be retained when not being powered.
In the DRAM, the transistor is responsible for the switch function and the capacitor is responsible for the data storage function. If power is not supplied, internal data within the DRAM are automatically lost. In addition, the SRAM has the transistor structure of a flip flop type. Data are stored according to the difference in the degree of driving between the transistors. Internal data within the SRAM are also automatically lost.
In contrast, the non-volatile memory that does not lose stored data even if power is not supplied has been developed in order for a developer to develop data or an operating system relating to the operation of the system and to supply the developed data or operating system. Examples of the non-volatile memory may include Programmable ROM (PROM), Electrically Programmable ROM (EPROM), and Electrically EPROM (EEPROM). Of them, there is a tendency that the demand for flash memory devices capable of programming and erasing data electrically has increased.
The flash memory device is an advanced type of EEPROM that can be erased electrically at high speed while not being removed from a circuit board. The flash memory device is advantageous in that it has a simple memory cell structure, has a low manufacturing cost per memory, and can retain data even if power is not supplied.
A general flash memory cell has a structure in which a tunnel oxide film, a floating gate, a gate dielectric film, and a control gate are sequentially laminated on a semiconductor substrate. The gate dielectric film is formed of an Oxide Nitride Oxide (ONO) film.
The properties of the flash memory cell may be varied significantly depending on the contact area of the floating gate and the semiconductor substrate with the tunnel oxide film therebetween, a thickness of the tunnel oxide film, the contact area of the floating gate and the control gate, and a thickness of the gate dielectric film.
Major characteristics of the flash memory cell may include the program rate, the erase rate, the distribution of program cells, and the distribution of erase cells. The reliability-related characteristics may include program/erase endurance, data retention, and so on.
In general, the program and erase rates (or speeds) are dependent on the ratio of a capacitance Ctunnel between the semiconductor substrate and the floating gate and a capacitance CONO between the floating gate and the control gate. In more detail, the program and erase rates are proportional to the coupling ratio coupling ratio. The coupling ratio can be expressed in the following equation.
      coupling    ⁢                  ⁢    ratio    =            C      ONO                      C        tunnel            +              C        ONO            
To obtain high program and erase rates at a predetermined operating voltage, it is necessary to secure a high coupling ratio. To this end, it is necessary to reduce Ctunnel or increase CONO.
As the design rule of the flash memory device decreases, the step of the floating gate is reduced in order to decrease the interference when implementing multi-level cells in devices of 50 nm or less.
If the step of the floating gate reduces, however, the overlapped area between the floating gate and the control gate decreases. Accordingly, CONO is lowered and the coupling ratio becomes small accordingly.
If the thickness of the gate dielectric film is decreased, CONO is increased and the coupling ratio can be improved accordingly. However, the flash memory device uses a high bias voltage unlike the DRAM. Accordingly, if the thickness of the gate dielectric film decreases, the leakage current is increased and program/erase endurance and data retention are degraded accordingly. It is therefore difficult to secure the reliability of devices.
Furthermore, in the case where the gate dielectric film is formed using a high dielectric layer having a high dielectric constant, the degradation of the reliability of devices, which is incurred by a reduction in the thickness of the gate dielectric film, can be prevented. However, a problem arises because it is difficult to meet the coupling ratio.